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Cypress Semiconductor /psoc63 /BLE /BLESS /LF_CLK_CTRL

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Interpret as LF_CLK_CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLE_LF_CLK)DISABLE_LF_CLK 0 (ENABLE_ENC_CLK)ENABLE_ENC_CLK 0M0S8BLESS_REV_ID

Description

BLESS LF clock control and BLESS revision ID indicator

Fields

DISABLE_LF_CLK

When set to 1, gates the LF clock input to the Link Layer. Ths is done for extended DSM mode where the DSM state machine needs to be forzen to prevent a default auto exit.
ENABLE_ENC_CLK

This bit is used to enable the clock to the encryption engine 0 - Disable the clock to ENC engine 1 - Enable the clock to ENC engine
M0S8BLESS_REV_ID

Indicates the m0s8bless IP revision.

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data